Wiring and manufacturing method thereof, semiconductor device comprising said wiring, and dry etching method

ABSTRACT

A dry etching method for forming tungsten wiring having a tapered shape and having a large specific selectivity with respect to a base film is provided. If the bias power density is suitably regulated, and if desired portions of a tungsten thin film are removed using an etching gas having fluorine as its main constituent, then the tungsten wiring having a desired taper angle can be formed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device having a circuitcomprised of a thin film transistor (hereafter referred to as TFT), anda method of manufacturing thereof. For example, the present inventionrelates to an electro-optical device typified by a liquid crystaldisplay panel, and to electronic equipment in which the electro-opticaldevice is installed as a part. In particular, the present inventionrelates to a dry etching method of etching a metallic thin film, and toa semiconductor device provided with a tapered shape wiring obtained bythe dry etching method.

Note that throughout this specification, the term semiconductor devicedenotes a general device which functions by utilizing semiconductorcharacteristics, and that electro-optical devices, semiconductorcircuits, and electronic equipments are all semiconductor devices.

2. Description of the Related Art

Techniques of structuring a thin film transistor (TFT) using asemiconductor thin film (having a thickness on the order of several nmto several hundred of nm) formed on a substrate having an insulatingsurface have been in the spotlight in recent years. Thin filmtransistors are widely applied to electronic devices such as an IC andan electro-optic device, and in particular, development of the TFT as aswitching element of a pixel display device is proceeding rapidly.

Conventionally, Al is often used in a TFT wiring material due to thingssuch as its ease of workability, its electrical resistivity, and itschemical resistance. However, when using Al in a TFT wiring, theformation of a protuberance such as a hillock or a whisker due to heattreatment, and the diffusion of aluminum atoms into a channel formingregion, causes poor TFT operation and a reduction of TFTcharacteristics. High heat resistance tungsten (W), with a relativelylow bulk resistivity of 5.5 μΩ·cm, can therefore be given as apreferable wiring material other than Al as a wiring material.

Further, in recent years, the demands of micro-processing techniqueshave become severe. In particular, with changes in high definition andlarge screens of a liquid crystal display, high selectivity in thewiring processing step as well as extremely strict control of line widthis required.

A general wiring process can be performed by wet etching using asolution or by dry etching using a gas. However, when consideringminiaturization of the wiring, maintenance of repeatability, reductionof waste, and decrease of cost, wet etching is unfavorable, andtherefore dry etching is considered favorable for wiring processing.

When processing tungsten (W) by dry etching, a mixed gas of SF₆ and Cl₂is generally used as an etching gas. While micro-processing with a largeetching rate in a short time is possible when this gas mixture is used,it is difficult to obtain a desirable tapered shape. In order to improvethe coverage of a lamination film formed on the wiring, there are casesin which the cross section of the wiring is made an intentional forwardtaper, depending upon the device structure.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a method of dry etchingfor patterning an etching layer made from tungsten (W) or a tungstencompound so as to give the cross section a forward tapered shape.Further, another object of the present invention is to provide a methodof controlling the dry etching method so as to have a uniform, arbitrarytaper angle over the entire etching layer, with no dependence uponlocation. In addition, another object of the present invention is toprovide a semiconductor device using a wiring having the arbitrary taperangle obtained from the above method, and a method of manufacturing thesemiconductor device.

A structure of the present invention disclosed in this specificationrelating to a wiring is:

-   -   a wiring having a tungsten film, a metallic compound film having        a tungsten compound as its main constituent, or a metallic alloy        film having a tungsten alloy as its main constituent,        characterized in that a taper angle a is within a range of 5° to        85°.

Further, another structure of the present invention relating to a wiringis:

-   -   a wiring having a lamination structure of laminated thin films        selected from the group consisting of: a tungsten film; a        metallic compound film having a tungsten compound as its main        constituent; and a metallic alloy film having a tungsten alloy        as its main constituent, characterized in that a taper angle a        is within a range of 5° to 85°.

In each of the above structures, the metallic alloy film ischaracterized in that it is an alloy film of one element, or a pluralityof elements, selected from the group consisting of: Ta; Ti; Mo; Cr; Nb;and Si, and tungsten.

Furthermore, the metallic compound film is characterized in that it is anitride film of tungsten in each of the above structures.

Moreover, in order to increase adhesion in each of the above structures,a silicon film having conductivity (for example, a phosphorous dopedsilicon film or a boron doped silicon film) may be formed as the lowestlayer of the wiring.

A structure of the present invention relating to a semiconductor deviceis:

-   -   a semiconductor device provided with a wiring made from a        tungsten film, a metallic compound film having a tungsten        compound as its main constituent, or a metallic alloy film        having a tungsten alloy as its main constituent, in which a        taper angle α is within a range of 5° to 85°.

Further, another structure of the present invention relating to asemiconductor device is:

-   -   a semiconductor device provided with a wiring made from a        lamination structure of laminated thin films selected from the        group consisting of: a tungsten film; a metallic compound film        having a tungsten compound as its main constituent; and a        metallic alloy film having a tungsten alloy as its main        constituent, in which a taper angle a is within a range of 5° to        85°.

In each of the above semiconductor related structures, the wiring ischaracterized in that it is a gate wiring of a TFT.

Furthermore, a structure of the present invention relating to a methodof manufacturing a wiring is:

-   -   a method of manufacturing a wiring, comprising:        -   a step of forming a metallic thin film on a base film;        -   a step of forming a resist pattern on the metallic thin            film; and        -   a step of forming the wiring, in which a taper angle a is            controlled in accordance with bias power density, by            performing etching of the metallic thin film having the            resist pattern.

Moreover, another structure of the present invention relating to amethod of manufacturing a wiring is:

-   -   a method of manufacturing a wiring, comprising:        -   a step of forming a metallic thin film on a base film;        -   a step of forming a resist pattern on the metallic thin            film; and        -   a step of forming the wiring, in which a taper angle is            controlled in accordance with flow rate of a gas containing            fluorine, by performing etching of the metallic thin film            having the resist pattern.

In each of the above structures relating to methods of manufacturing awiring:

-   -   the method of manufacturing is characterized in that:        -   the etching is performed using an etching gas comprised of a            mixed gas of a first reaction gas containing fluorine and a            second reaction gas containing chlorine; and        -   the specific selectivity in the etching gas between the base            film and the metallic thin film is greater than 2.5.

Further, the metallic thin film in each of the above structures relatingto methods of manufacturing a wiring is characterized in that it is athin film, or a lamination film of thin films, selected from the groupconsisting of: a tungsten film; a metallic compound film having atungsten compound film as its main constituent; and a metallic alloyfilm having a tungsten alloy as its main constituent.

A structure of the present invention relating to a method of dry etchingis:

-   -   a method of dry etching having the removal by an etching gas of        a desired portion of a thin film selected from the group        consisting of: a tungsten film; a metallic compound film having        a tungsten compound film as its main constituent; and a metallic        alloy film having a tungsten alloy as its main constituent,        characterized in that the etching gas is a mixed gas of a first        reaction gas containing fluorine and a second reaction gas        containing chlorine.

In the above structure of the present invention relating to the dryetching method, the first reaction gas is characterized in that it is agas selected from the group consisting of CF₄, C₂F₆, and C₄F₈.

Further, in the above structure of the present invention relating to thedry etching method, the second reaction gas is characterized in that itis a gas selected from the group consisting of Cl₂, SiCl₄, and BCl₃.

Moreover, the etching method is characterized in that it uses an ICPetching device in the above structure of the present invention relatedto a method of dry etching.

The above structure of the present invention relating to the dry etchingmethod is further characterized in that a taper angle a is controlled inaccordance with the bias power density of the ICP etching device.

Another structure of the present invention relating to a method of dryetching is:

-   -   a method of dry etching characterized in that a taper angle of        an inside sidewall of a formed hole or recess is controlled in        accordance with bias power density.

In addition, another structure of the present invention relating to amethod of dry etching is:

-   -   a method of dry etching characterized in that a taper angle of        an inside sidewall of a formed hole or recess is controlled in        accordance with specific gas flow rate.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a diagram showing the dependence of a taper angle α on biaspower;

FIG. 2 is a diagram showing the dependence of the taper angle α onspecific CF₄ flow rate;

FIG. 3 is a diagram showing the dependence of the taper angle α onspecific (W/resist) selectivity;

FIG. 4 is a drawing showing a plasma generation mechanism of an ICPetching device;

FIG. 5 is a diagram showing a multi-spiral coil method ICP etchingdevice;

FIGS. 6A and 6B are explanatory diagrams for a taper angle α;

FIGS. 7A to 7C are cross sectional SEM photographs of wirings;

FIGS. 8A and 8B are cross sectional SEM photographs of wirings;

FIGS. 9A and 9B are diagrams showing the dependence of etching rate andspecific (W/resist) selectivity on bias power;

FIGS. 10A and 10B are diagrams showing the dependence of etching rateand specific (W/resist) selectivity on specific CF₄ flow rate;

FIGS. 11A and 11B are diagrams showing the dependence of etching rateand specific (W/resist) selectivity on ICP power;

FIG. 12 is a cross sectional diagram of an active matrix type liquidcrystal display device;

FIG. 13 is a cross sectional diagram of an active matrix type liquidcrystal display device;

FIG. 14 is a cross sectional diagram of an active matrix type liquidcrystal display device;

FIGS. 15A to 15F are cross sectional diagrams of wirings;

FIG. 16 is a diagram showing the structure of an active matrix type ELdisplay device;

FIG. 17 is a diagram showing a perspective view of an AM-LCD;

FIGS. 18A to 18F are diagrams showing examples of electronic equipment;and

FIGS. 19A to 19D are diagrams showing examples of electronic equipment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment Mode

The preferred embodiments of the present invention are explained usingFIGS. 1 to 8B.

An ICP (inductively coupled plasma) etching device which uses a highdensity plasma is used in the present invention. Explained simply, theICP etching device is a device which achieves a plasma density equal toor greater than 10¹¹/cm³ by inductively coupling RF power in a plasma atlow pressure, and performs etching with a high selectivity and at a highetching rate.

First, the plasma generation mechanism of the ICP dry etching device isexplained in detail, using FIG. 4.

A simplified structure diagram of an etching chamber is shown in FIG. 4.An antenna coil 12 is arranged on a quartz substrate 11 in the upperportion of the chamber, and the coil 12 is connected to an RF powersource 14 through a matching box 13. Further, an RF power source 17 isconnected through a matching box 16 to a lower electrode 15 of asubstrate arranged on the opposing side.

If an RF current is applied to the antenna coil 12 over the substrate,then an RF current J flows in the θ direction and a magnetic field Bdevelops in the Z direction.μ₀J=rot B

An induced electric field E develops in the θ direction in accordancewith Faraday's law of electromagnetic induction.−∂B/∂t=rot E

Electrons are accelerated in the θ direction in the induced electricfield E and collide with gas molecules, generating a plasma. Thedirection of the induced electric field is the θ direction, andtherefore the probability of electric charge disappearing by chargedparticles colliding with the etching chamber walls and the substrate isreduced. A high density plasma can therefore be generated at even a lowpressure on the order of 1 Pa. Further, there is almost no magneticfield B downstream, and consequently the plasma becomes a high densityplasma spread out in a sheet shape.

By regulating the RF power applied to both the antenna coil 12 (ICPpower is applied) and the lower electrode 15 of the substrate (biaspower is applied), it is possible to control the plasma density and theauto-bias voltage independently. Further, it is possible to vary thefrequency of the applied RF power depending on the material of the pieceto be processed.

In order to obtain a high density plasma with the ICP etching device, itis necessary for the RF current J to flow with little loss in theantenna coil 12, and in order to make a large surface area, theinductance of the antenna coil 12 must be reduced. An ICP etching devicewith a multi-spiral coil 22, in which the antenna is partitioned, hastherefore been developed, as shown in FIG. 5. Reference numeral 21denotes a quartz substrate, reference numerals 23 and 26 denote matchingboxes, and 24 and 27 denote RF power sources in FIG. 5. Further, a lowerelectrode 25 for holding a substrate 28 is formed through an insulator29 in the lower portion of the chamber. If an etching device using ICPin which the multi-spiral coil is applied is used, then it is possibleto preform good etching of the above heat resistant conducting material.

The applicants of the present invention performed several experimentsusing the multi-spiral ICP etching device (Matsushita Electric modelE645) by varying the etching conditions.

The etching test piece used in the experiments is explained first. Abase film (200 nm thickness) is formed from a silicon oxynitride film onan insulating substrate (Corning #1737 glass substrate), and a metalliclamination film is formed thereon by sputtering. A tungsten targethaving a purity equal to or greater than 6N is used. Further, a singlegas such as argon (Ar), krypton (Kr), or xenon (Xe), or a mixture ofsuch gasses, may be used. Note that film deposition conditions such assputtering power, gas pressure, and substrate temperature may besuitably controlled by the operator.

The metallic lamination film has a tungsten nitride film (filmthickness: 30 nm) denoted by WN_(x) (where 0<x<1) as a lower layer, andhas a tungsten film (370 nm thickness) as an upper layer.

The metallic lamination film thus obtained contains almost no impurityelements, and in particular, the amount of oxygen contained can be madeequal to or less than 30 ppm. The electrical resistivity can be madeequal to or less than 20 μΩ·cm, typically between 6 and 15 μΩ·cm.Further, the film stress can be made from −5×10⁹ dyn/cm² to 5×10⁹dyn/cm².

Note that throughout this specification, a silicon oxynitride film is aninsulating film denoted by SiOxNy, and denotes an insulating filmcontaining silicon, oxygen, and nitrogen in predetermined ratios.

Patterning experiments of the metallic lamination film were performed onthe etching test piece using the multi-spiral coil ICP etching device.Note that when performing dry etching, it goes without saying thatresist is used and patterned into a predetermined shape, forming aresist mask pattern (film thickness: 1.5 μm).

A cross sectional diagram of a model of the etching test piece beforeetching processing is shown in FIG. 6A. Reference numeral 601 denotes asubstrate, reference numeral 602 denotes a base film, 603 a and 603 bdenote a metallic lamination film (film thickness X=400 nm), and 604 aand 604 b denote a resist mask pattern (film thickness Y=1.5 μm) in FIG.6A. Further, FIG. 6B is a diagram showing the state after etchingprocessing.

Note that, as shown in FIG. 6B, taper angle denotes an angle α between atapered portion (inclined portion) of the cross sectional shape of thewiring 603 and the base film 602 throughout this specification. Further,the taper angle can be defined as tan α=X/Z, using the width of thetapered portion Z and the film thickness X.

The applicants of the present invention varied several conditions of thedry etching and observed the cross sectional shape of the wiring.

[Experiment 1]

FIG. 1 is a diagram showing the dependence of the taper angle α on thebias power. An experiment was performed with a 13.56 MHz bias power at20 W, 30 W, 40 W, 60 W, and 100 W; namely, with bias power densities(W/cm²) of 0.128, 0.192, 0.256, 0.384, and 0.64. Note that the lowerelectrode was 12.5 cm×12.5 cm. Further, the resist film thickness was1.5 μm, the gas pressure was 1.0 Pa, and the gas composition wasCF₄/Cl₂=30/30 sccm (note that sccm denotes the volume flow rate(cm³/min) at standard conditions). In addition, the ICP power was 500 W;namely, the ICP power density was 1.02 W/cm². Note that, throughout thisspecification, the value of ICP power divided by ICP area (25 cmdiameter) is taken as the ICP power density (W/cm²).

From FIG. 1, it can be understood that the higher the bias powerdensity, the smaller the taper angle α becomes. Further, by simplyregulating the bias power density, the desired taper angle α=5° to 85°(preferably in the range of 20° to 70°) can be formed.

Note that a SEM photograph of a cross section when the bias power wasset to 20 W (bias power density: 0.128 W/cm²) is shown in FIG. 7A; a SEMphotograph of a cross section when the bias power was set to 30 W (biaspower density: 0.192 W/cm²) is shown in FIG. 7B; a SEM photograph of across section when the bias power was set to 40 W (bias power density:0.256 W/cm²) is shown in FIG. 7C; a SEM photograph of a cross sectionwhen the bias power was set to 60 W (bias power density: 0.384 W/cm²) isshown in FIG. 8A; and a SEM photograph of a cross section when the biaspower was set to 100 W (bias power density: 0.64 W/cm²) is shown in FIG.8B. It can be observed from each SEM photograph shown in FIGS. 7A to 8Bthat the taper angle α is formed within the range of 20° to 70°, andthat the taper angle α can be controlled by changing the bias powerdensity.

It is thought that this is because the selectivity between tungsten andresist becomes small, and a retreating phenomenon of the resistdevelops.

[Experiment 2]

FIG. 2 is a diagram showing the dependence of the taper angle α on thespecific flow rate of CF₄. Experiments were performed with gascomposition ratios of CF₄/Cl₂=20/40 sccm, 30/30 sccm, and 40/20 sccm.The gas pressure was 1.0 Pa, the bias power density was 0.128 W/cm², theresist film thickness was 1.5 μm, and the ICP power was 500 W (ICP powerdensity: 1.02 W/cm²).

From FIG. 2, it is understood that the larger the specific flow rate ofCF₄, the larger the selectivity between tungsten and resist, and thelarger the taper angle α of the wiring becomes. Further, the roughnessof the base film becomes less. Regarding the roughness of the base film,it is thought that the reason is due to weak anisotropy of the etchingcaused by an increase in the flow rate of CF₄ (decrease in the flow rateof Cl₂). Furthermore, by simply regulating the specific flow rate ofCF₄, the desired taper angle α=5° to 85° (preferably in the range of 60°to 80°) can be formed.

[Experiment 3]

An experiment was performed by setting the 13.56 MHz, ICP power to 400W, 500 W, and 600 W; namely, by setting the ICP power density to 0.82,1.02, and 1.22. The bias power was 20 W (bias power density: 0.128W/cm²), the resist film thickness was 1.5 μm, the gas pressure was 1.0Pa, and the gas composition was CF₄/Cl₂=30/30 sccm.

The etching rate of tungsten becomes larger as the ICP power densitygets larger, but the etching rate distribution becomes worse. Further,there are no particular changes seen in the taper angle.

[Experiment 4]

An experiment was performed with gas pressures of 1.0 Pa and 2.0 Pa. TheICP power was 500 W (ICP power density: 1.02 W/cm²), the gas compositionwas CF₄/Cl₂=30/30 sccm, the bias power was 20 W (bias power density:0.128 W/cm²), and the resist film thickness was 1.5 μm.

The tungsten etching rate becomes faster along with higher vacuum, andthe anisotropy also becomes stronger. Further, the taper becomes areverse taper shape at 2.0 Pa.

[Experiment 5]

An experiment was performed with the total flow rate of the etching gasset to 60 sccm and 120 sccm. The gas pressure was 1.0 Pa, the ICP powerwas 500 W (ICP power density: 1.02 W/cm²), the gas composition wasCF₄/Cl₂=30/30 sccm, the bias power was 20 W (bias power density: 0.128W/cm²), and the resist film thickness was 1.5 μm.

The etching rate become a little larger for the case of the larger totalflow rate of the etching gas.

From the results of the above experiments, it is thought that there is adependence of the taper angle on the selectivity between tungsten andresist because the taper angle is mainly influenced by the bias powerdensity conditions. The dependence of the taper angle on the selectivitybetween tungsten and resist is shown in FIG. 3.

Changes in bias power density have a larger influence on the selectivitybetween tungsten and resist than on the etching rate of tungsten, and ifthe bias power density is made large, then there is a tendency for theselectivity between tungsten and resist to fall. The dependence ofetching rates of tungsten and resist on bias power density is shown inFIG. 9A, while the dependence of the selectivity between tungsten andresist on bias power density is shown in FIG. 9B.

Namely, as shown in FIG. 6A and in FIG. 6B, resist is etched at the sametime as tungsten is etched, and therefore if the selectivity betweentungsten and resist is large, the taper angle becomes large, and if theselectivity between tungsten and resist is small, the taper anglebecomes small.

Further, if the specific flow rate of CF₄ gas is made smaller in thesame way, then there is a tendency for the selectivity between tungstenand resist to fall. FIG. 10A shows the dependance of etching rates oftungsten and resist on specific CF₄ gas flow rate, and FIG. 10B showsthe dependence of the selectivity between tungsten and resist onspecific CF₄ gas flow rate.

Further, the dependence of etching rates of tungsten and resist on ICPpower density is shown in FIG. 11A, and the dependence of theselectivity between tungsten and resist on ICP power density is shown inFIG. 11B.

A test piece in which a base film (200 nm thickness) made from a siliconoxynitride film formed on an insulating substrate, and a metalliclamination film (a lamination film of a tungsten nitride film and atungsten film) formed on the base film is used as a test piece foretching in each of the above experiments, but with the presentinvention, it is also possible to apply a thin film, or a laminationstructure of a lamination of thin films, selected from the groupconsisting of a tungsten film, a metallic compound film having atungsten compound as its main constituent, and a metallic alloy filmhaving a tungsten alloy as its main constituent. Note, however, thatfilms in which the selectivity with the base film is equal to or lessthan 2.5, and cases in which the etching rate is extremely small can notbe applied. For example, a W—Mo alloy film (having a ratio of W:Mo=52:48by weight) possesses a selectivity with the base film (SiO_(x)N_(y))which is equal to or less than approximately 1.5, and the etching rateis small at approximately 50 nm/min, and therefore it is not suitablefrom a workability standpoint.

A W film is shown as one example here, but for generally known heatresistant conducting materials (such as Ta, Ti, Mo, Cr, Nb, and Si),when an ICP etching device is used, the edge of a pattern can easily bemade into a tapered shape. For example, if a Ta film with an etchingspeed of 140 to 160 nm/min and a selectivity of 6 to 8 is chosen, it hassuperior values in comparison with the W film having an etching speed of70 to 90 nm/min and a selectivity of 2 to 4. Therefore, from thestandpoint of workability, the Ta film is also suitable, but the Ta filmhas a resistivity of 20 to 30 μΩ·cm, which is little high in comparisonwith the resistivity of the W film, from 10 to 16 μΩ·cm, and thisbecomes a problem.

Further, a gas mixture of CF₄ gas and Cl₂ gas is used as the etching gasfor the above dry etching, but there are no particular limitations onthis, and it is also possible to use a mixed gas of a reactive gascontaining fluorine selected from the group consisting of C₂F, and C₄F₈,and a gas containing chlorine selected from the group consisting of Cl₂,SiCl₄, and BCl₃.

In addition, there are no particular limitations on the etchingconditions of the present invention, and for a case of using, forexample, an ICP etching device (Matsushita Electric mode: E645) andusing carbon tetrafluoride gas (CF₄) and chlorine (Cl₂), the etchingconditions may be suitably determined by the operator within thefollowing ranges: etching gas total flow 60 to 120 sccm rate: specificetching gas flow CF₄/Cl₂ = 30/30 sccm to 50/10 sccm rate: gas pressure:1.0 Pa to 2.0 Pa (pressure of etching gas atmosphere) ICP power density:0.61 W/cm² to 2.04 W/cm² (ICP power: 300 W to 1000 W), frequency of 13MHz to 60 MHz bias power density: 0.064 W/cm² to 3.2 W/cm² (bias power:10 W to 500 W), frequency of 100 kHz to 60 MHz, preferably 6 MHz to 29MHz substrate temperature: 0° C. to 80° C., preferably 70° C. ± 10° C.

Note that, throughout this specification, the term “electrode” refers toa portion of the term “wiring”, and denotes a location for performingelectrical connection to another wiring, or a location for intersectionwith a semiconductor layer. Therefore, for convenience, while the use of“wiring” and “electrode” is properly divided, “wiring” is normallyincluded for sentences using “electrode”.

A detailed explanation of the present invention, having the abovestructure, is made using the embodiments shown below.

Embodiment 1

Embodiment 1 of the present invention is explained using FIGS. 12 and13. An active matrix substrate having a pixel TFT and a storagecapacitor of a pixel portion, and a driver circuit TFT formed in theperiphery of the pixel portion manufactured at the same time, isexplained here.

The structure of embodiment 1 has TFTs formed on a substrate 101 havingan insulating surface, as shown in FIG. 12. It is preferable to use aglass substrate or a quartz substrate for the substrate 101. It is alsopossible to use a plastic substrate, provided that the heat resistanceis acceptable. In addition, if a reflecting type display device is beingmanufactured, then a silicon substrate, a metallic substrate, or astainless steel substrate, having an insulating film formed on eachsurface, may also be used as the substrate.

The surface of the substrate 101 on which the TFTs are formed has a basefilm 102 made from an insulating film containing silicon (a generic nameindicating a silicon oxide film, a silicon nitride film, or a siliconoxynitride film throughout this specification). For example, alamination film of a silicon oxynitride film 102 a with a thickness of10 to 200 nm (preferably between 50 and 100 nm) and manufactured byplasma CVD from SiH₄, NH₃, and N₂O, and a hydrogenated siliconoxynitride film 102 b with a thickness of 50 to 200 nm (preferablebetween 100 and 150 nm) and manufactured similarly from SiH₄, N₂O, andH₂, is formed. A two-layer structure is shown for the base film 102here, but a single layer insulating film or a lamination film havingmore than two layers may also be formed.

Further, active layers of the TFTs are formed on the base film 102. Acrystalline semiconductor film, obtained from crystallizing asemiconductor film having an amorphous structure, on which patterning isthen performed is used as the active layers. A known technique, forexample, laser annealing or thermal annealing (solid phase growthmethods), rapid thermal annealing (RTA method), or a crystallizationmethod using a catalytic element, in accordance with the techniquedisclosed in Japanese Patent Application Laid-open No. Hei 7-130652, maybe used as the crystallization method. Note that amorphous semiconductorfilms and microcrystalline semiconductor films exist as semiconductorfilms having an amorphous structure, and that a compound semiconductorfilm having an amorphous structure, such as an amorphous silicongermanium film, may also be applied.

A gate insulating film 130 covering the above TFT active layers isformed by using plasma CVD or sputtering from an insulating filmcontaining silicon with a thickness of 40 to 150 nm. A 120 nm thicksilicon oxynitride film is formed in embodiment 1. Further, a siliconoxynitride film manufactured by doping O₂ into SiH₄ and N₂O has areduced fixed electric charge density within the film, and therefore itis a desirable material for use. The gate insulating film is not limitedto this type of silicon oxynitride film, of course, and other insulatingfilms containing silicon may be used in either a single layer or alamination structure.

A heat resistant conducting material is used for gate electrodes 118 to122 and a capacitor electrode 123 formed on the gate insulating film,which have a lamination structure of a conducting layer (A) made from aconducting metallic nitride film and a conducting layer (B) made from ametallic film. The conducting layer (B) may be formed from an elementselected from the group consisting of Ta, Ti, and W, or from an alloyhaving one of the above elements as its main constituent, or from analloy film of a combination of the above elements. In embodiment 1, aconducting lamination film of a 50 nm thick WN film formed as theconducting layer (A) and a 250 nm thick W film formed as the conductinglayer (B) by sputtering which uses a W target having a purity of 6 N andin which Ar gas and nitrogen (N₂) gas is introduced, is patterned,completing the gate electrodes 118 to 122 and the capacitor electrode123. Note that etching is performed so that a tapered portion is formedin the edges of the gate electrodes 118 to 123. The etching process isperformed using an ICP etching device. Details of this technique are asshown in the embodiment mode of the present invention. In embodiment 1,etching is performed using a gas mixture of CF₄ and Cl₂ for the etchinggas, with the flow rates each to 30 sccm, the ICP power density set to3.2 W/cm² (frequency: 13.56 MHz), the bias power density set to 0.224W/cm² (frequency: 13.56 MHz), and a gas pressure of 1.0 Pa. By usingthese etching conditions, a tapered portion is formed in the edgeportions of the gate electrodes 118 to 122 and the capacitor electrode123, in which the thickness increases gradually from the edge portiontoward the inside. The angle can be made from 25 to 35°, preferably 30°.

Note that, in order to perform etching so as not to leave any residuewhen forming the gate electrodes 118 to 122 and the capacitor electrode123 which have the tapered shape, overlap etching is performed, in whichthe etching time is increased on the order of 10 to 20%, and thereforethe gate insulating film 130 has a portion which becomes thin inpractice.

Further, in embodiment 1, in order to form LDD regions, an impurityelement for imparting n-type or p-type conductivity is added into theactive layers in a self-aligning manner by ion doping with the gateelectrodes 118 to 122 having the tapered portions in their edges, asmasks. Furthermore, in order to form suitable, desired LDD regions, animpurity element for imparting n-type or p-type conductivity is added tothe active layers by ion doping with a resist pattern as a mask.

A structure having a channel forming region 206, an LDD region 207overlapping with the gate electrode, a source region 208 composed of ahigh concentration p-type impurity region, and a drain region 209 in theactive layer is thus formed in a first p-channel TFT (A) 200 a of thedriver circuit. A first n-channel TFT (A) 201 a has a channel formingregion 210, an LDD region 211 made from a low concentration n-typeimpurity region overlapping the gate electrode 119, a source region 212formed by a high concentration n-type impurity region, and a drainregion 213 in the active layer. The LDD region overlapping the gateelectrode 119, taken as L_(ov), has a length of 0.1 to 1.5 μm,preferably between 0.3 and 0.8 μm, in the longitudinal direction of thechannel for a channel length of 3 to 7 μm. The length of L_(ov) controlsthe thickness of the gate electrode 119 and the angle of the taperedportion.

Further, the active layer in a second p-channel TFT (A) 202 a of thedriver circuit similarly has a channel forming region 214, an LDD region215 overlapping the gate electrode 120, a source region 216 formed by ahigh concentration p-type impurity region, and a drain region 217 in theactive layer. In a second n-channel TFT (A) 203 a, the active layer hasa channel forming region 218, an LDD region 219 overlapping the gateelectrode 121, a source region 220 formed by a high concentration n-typeimpurity region, and a drain region 221. The LDD region 219 has the samestructure as the LDD region 211. A pixel TFT 204 has channel formingregions 222 a and 222 b, LDD regions 223 a and 223 b formed by lowconcentration n-type impurity regions, and source or drain regions 225to 227 formed by high concentration n-type impurity regions in theactive layer. The LDD regions 223 a and 223 b have the same structure asthe LDD region 211. In addition, a storage capacitor 205 is formed fromthe capacitor wiring 123, the gate insulating film, and semiconductorlayers 228 and 229 connected to the drain region 227 of the pixel TFT204. In FIG. 12, the n-channel TFT and the p-channel TFT of the drivercircuit have a single gate structure in which one gate electrode isprovided between the source and drain pair, and the pixel TFT has adouble gate structure, but all of the TFTs may be given a single gatestructure, and a multi-gate structure in which a plurality of gateelectrodes are provided between one source and drain pair will not causeany hindrance.

Further, there is a protecting insulating film 142 covering the gateelectrode and the insulating film 130. The protecting insulating filmmay be formed by a silicon oxide film, a silicon oxynitride film, asilicon nitride film, or by a lamination film of a combination of thesefilms.

In addition, there is an interlayer insulating film 143 made from anorganic insulating material covering the protecting insulating film 142.Materials such as polyimide, acrylic, polyamide, polyimide amide, andBCB (benzocyclobutene) can be used as an organic resin material.

Moreover, there are source wirings and drain wirings on the interlayerinsulating film 143 for connecting to the source regions and drainregions formed on the respective active layers, through contact holes.Note that the source wirings and the drain wirings have a laminationstructure of a lamination film of Ti and aluminum, denoted by referencenumerals 144 a to 154 a, and a transparent conducting film, denoted byreference numerals 144 b to 154 b. Further, the drain wirings 153 a and153 b also function as pixel electrodes. An indium oxide and zinc oxidealloy (In₂O₃—ZnO) and zinc oxide (ZnO) are suitable materials for thetransparent conducting film, and in order to additionally increase thetransmissivity and the conductivity, materials such as zinc oxide inwhich gallium (Ga) has been added (ZnO:Ga) can be ideally used.

With the above construction, the structure of TFTs constituting eachcircuit is optimized in accordance with the specifications required bythe pixel TFT and the driver circuit, and it is possible to increase theoperating performance and the reliability of a semiconductor device. Inaddition, by forming the gate electrodes with a conducting materialhaving heat resistance, the activation of the LDD regions and the sourceregions or drain regions becomes easy.

Additionally, during formation of the LDD region overlapping the gateelectrode through the gate insulating film, by forming the LDD regionwhich possesses a concentration gradient of an impurity element addedwith the aim of controlling the conductivity type, it can be expectedthat the electric field relaxation effect will be increased,particularly in the vicinity of the drain region.

The active matrix substrate shown in FIG. 12 can be applied as is to atransmitting type liquid crystal display device.

An active matrix type liquid crystal display device, in which the activematrix substrate shown in FIG. 12 is applied, is explained next usingFIG. 13.

First, a resin film on the active matrix substrate is patterned, formingrod shape spacers 405 a to 405 e and 406. The placement of the spacersmay be arbitrarily determined. Note that a method of forming the spacersby dispersing grains of several μm may also be used.

An alignment film 407 is formed next in the pixel portion of the activematrix substrate from a material such as a polyimide resin in order toorient the liquid crystals. After forming the alignment film, a rubbingprocess is performed, orienting the liquid crystal molecules so as topossess a certain fixed pre-tilt angle.

A light shielding film 402, a transparent conducting film 403, and analignment film 404 are formed in an opposing substrate 401 on theopposite side. The light shielding film 402 is formed with a thicknessof 150 to 300 nm by a film such as a Ti film, a Cr film, or an Al film.The active matrix substrate, on which the pixel portion and the drivercircuit are formed, and the opposing substrate are then joined togetherby a sealing member 408.

Afterward, a liquid crystal material 409 is injected between bothsubstrates. A known liquid crystal material may be used for the liquidcrystal material. For example, in addition to a TN liquid crystal, athresholdless antiferroelectric mixed liquid crystal, indicating anelectro-optical response in which the transmissivity changescontinuously with respect to an electric field, can also be used.V-shape electro-optical response characteristics are displayed in somethresholdless antiferroelectric mixed liquid crystal. The reflectingtype active matrix type liquid crystal display device shown in FIG. 13is thus completed.

Embodiment 2

Using FIG. 14, embodiment 2 shows an example of manufacturing a displaydevice using a bottom gate TFT which differs from embodiment 1 (a topgate TFT) above.

First, a metallic lamination film is formed by sputtering on aninsulating substrate 1801. The metallic lamination film has a tungstennitride film for a bottom layer and a tungsten film for a top layer.Note that a base film contacting the substrate may also be formed, froma film such as a silicon oxynitride film denoted by SiO_(x)N_(y). Next,a resist mask for obtaining a desired gate wiring pattern is formed byphotolithography.

It is necessary for constituents such as a gate insulating film and achannel forming region to be formed on the gate wiring in the bottomgate TFT. In order to increase the characteristics of the bottom gatestructure TFT, the coverage of the films formed on the gate wiring, andthe voltage resistance of the gate insulating film, it is preferablethat the taper angle of gate wirings 1802 to 1805 be equal to or lessthan 60°, more preferably equal to or less than 40°.

Next, as shown above in the embodiment mode of the present invention,the taper angle of the gate wirings 1802 to 1805 is made equal to orless than 60°, more preferably equal to or less than 40°, using an ICPetching device and selecting suitably the bias power and the specificgas flow rate. Known techniques may be used for subsequent processing,and there are no particular limitations imposed.

In FIG. 14, reference numeral 1814 denotes a CMOS circuit, referencenumeral 1815 denotes an n-channel TFT, 1816 denotes a pixel TFT, 1817denotes an interlayer insulating film, 1818 a denotes a pixel electrode,and 1818 b denotes an ITO film. The ITO film 1818 b is formed in orderto be connected to an external terminal such as an FPC 1823 throughadhesive 1822. Further, reference numeral 1819 denotes a liquid crystalmaterial, and 1820 denotes an opposing electrode. In addition, referencenumeral 1801 denotes the first substrate, 1808 denotes a sealing region,1807, and 1809 to 1812 denote rod shape spacers, and 1821 denotes asecond substrate.

Note that it is possible to freely combine embodiment 2 with embodiment1.

Embodiment 3

Examples of various wiring structures formed on an insulating surface byutilizing the present invention are shown in FIGS. 15A to 15F. A crosssectional diagram of a single layer structure wiring made from amaterial 1501 having tungsten as its main constituent and formed on afilm (or a substrate) 1500 having an insulating surface is shown in FIG.15A. This wiring is formed by patterning a film formed by sputteringwhich uses a target with a purity of 6N (99.9999%) and a single gas,argon (Ar), as the sputtering gas. Note that the stress is controlled bysetting the substrate temperature equal to or less than 300° C., and bysetting the sputtering gas pressure equal to or greater than 1.0 Pa, andthat other conditions (such as the sputtering power) may be suitablydetermined by the operator.

When performing the above patterning, a taper angle α is controlled bythe method shown in the embodiment mode of the present invention, inaccordance with the bias power density, for example.

The cross sectional shape of the wiring 1501 thus obtained has thedesired taper angle a. Further, there are almost no impurity elementscontained in the wiring 1501, and in particular, the amount of oxygencontained can be made equal to or less than 30 ppm, and the electricalresistivity can be made equal to or less than 20 μΩ·cm, typicallybetween 6 μΩ·cm and 15 μΩ·cm. Further, the film stress can be controlledwithin the range of −5×10¹⁰ to 5×10¹⁰ dyn/cm².

FIG. 15B shows a two-layer structure, similar to the gate electrode ofembodiment 1. Note that tungsten nitride (WN_(x)) is taken as the lowerlayer, and that tungsten is taken as the upper layer. Also note that thethickness of a tungsten nitride film 1502 may be set from 10 to 50 nm(preferably between 10 and 30 nm), and that the thickness of a tungstenfilm 1503 may be set from 200 to 400 nm (preferably between 250 and 350nm). The two films are laminated in succession, without exposure to theatmosphere, using sputtering in embodiment 3.

FIG. 15C is an example of covering a wiring 1504, made from a materialhaving tungsten as its main constituent and formed on the film (orsubstrate) 1500 which possesses an insulating surface, by an insulatingfilm 1505. The insulating film 1505 may be formed by a silicon nitridefilm, a silicon oxide film and a silicon oxynitride film SiO_(x)N_(y)(where 0<x, and y<1), or by a lamination film of a combination of thesefilms.

FIG. 15D is an example of covering the surface of a wiring 1506 madefrom a material having tungsten as its main constituent, and formed onthe film (or substrate) 1500 having an insulating surface, by a tungstennitride film 1507. Note that if a nitrating process, such as plasmanitrating, is performed on the wiring in the state of FIG. 15A, then thestructure of FIG. 15D can be obtained.

FIG. 15E is an example of surrounding a wiring 1509 made from a materialhaving tungsten as its main constituent, and formed on the film (orsubstrate) 1500 having an insulating surface, by tungsten nitride films1510 and 1508. Note that if a nitrating process, such as plasmanitrating, is performed on the wiring in the state of FIG. 15B, then thestructure of FIG. 15E can be obtained.

FIG. 15F is an example of covering by an insulating film 1511, afterforming the state of FIG. 15E. The insulating film 1511 may be formed bya silicon nitride film, a silicon oxide film, a silicon oxynitride film,or a lamination film of a combination of these films.

The present invention can thus be applied to various wiring structures.It is possible to freely combine the constitution of embodiment 3 withthe constitutions shown in embodiment 1 and in embodiment 2.

Embodiment 4

A case of applying the present invention to a reflection type liquidcrystal display device manufactured over a silicon substrate isexplained in Embodiment 4. As a substitute for the active layercomprising a crystalline silicon film in Embodiment 1, an impurityelement for imparting n-type or p-type conductivity is added directlyinto a silicon substrate (silicon wafer), and the TFT structure may berealized. Further, the structure is reflection type, and therefore ametallic film having a high reflectivity (for example, aluminum, silver,or an alloy of these (an Al—Ag alloy)) and the like may be used as apixel electrode.

Note that it is possible to freely combine the constitution ofEmbodiment 4 with the constitution of any of embodiments 1 to 3.

Embodiment 5

It is possible to use the present invention when forming an interlayerinsulating film over a conventional MOSFET, and then forming a TFT onthat. In other words, it is possible to realize a semiconductor devicewith a three dimensional structure. Further, it is possible to use anSOI substrate such as SIMOX, Smart-Cut (a trademark of SOITECcorporation), or ELTRAN (a trademark of Cannon, Inc.) Note that it ispossible to freely combine the structure of embodiment 5 with thestructure of any of embodiments 1 to 4.

Embodiment 6

It is possible to apply the present invention to an active matrix ELdisplay. An example of this is shown in FIG. 16.

FIG. 16 is a circuit diagram of an active matrix EL display. Referencenumeral 81 denotes a pixel portion, and an x-direction driver circuit 82and a y-direction driver circuit 83 are formed in its peripheral.Further, each pixel in the pixel portion 81 comprises a switching TFT84, a capacitor 85, a current controlling TFT 86, and an organic ELelement 87, and the switching TFT 84 is connected to x-direction signallines 88 a (or 88 b) and to y-direction signal lines 89 a (or 89 b, 89c). Furthermore, power supply lines 90 a and 90 b are connected to thecurrent controlling TFT 86.

In an active matrix EL display of the present embodiment, TFTs used inan x-direction driver circuit 82, a y-direction driver circuit 83 andcurrent controlling TFT 86 are formed by combining p-channel TFT 200 aor 202 a of FIG. 12 and n-channel TFT 201 a or 203 a of FIG. 12. TheTFTs for switching TFT 84 are formed by n-channel TFT 204 of FIG. 12.

It is possible to freely combine the active matrix EL display of thepresent invention with any constitution of Embodiments 1 to 5.

Embodiment 7

The structure of the active matrix liquid crystal display device shownin FIG. 13 of the Embodiment 1 is described with reference to theperspective view of FIG. 17. The active matrix substrate (the firstsubstrate) comprises a pixel portion 802, a gate side driver circuit 803and a source side driver circuit 804 formed over a glass substrate 801.The pixel TFT 805 of the pixel portion (corresponding to pixel TFT 204of FIG. 13) is an n-channel TFT, and is connected to a pixel electrode806 and a storage capacitor 807 (corresponding to storage capacitor 205of FIG. 13).

The driver circuits disposed in the periphery are comprised of a CMOScircuit as its base. The gate side driver circuit 803 and the sourceside driver circuit 804 are connected to the pixel portion 802 throughthe gate wiring 808 and the source wiring 809 respectively. Further,input-output wiring (connecting wiring) 812 and 813 are disposed in theexternal input-output terminal 811 connected to the FPC 810 fortransmitting signals to the driver circuits. Reference numeral 814 is anopposing substrate (the second substrate).

Note that though the semiconductor device shown in FIG. 17 is referredto as active matrix liquid crystal display device in this Specification,the liquid crystal panel furnished with an FPC as shown in FIG. 17 isreferred to as a liquid crystal module in general. Accordingly it isacceptable to refer an active matrix liquid crystal display device ofthis Embodiment as a liquid crystal module.

Embodiment 8

TFTs manufactured by implementing the present invention can be used forvarious electro-optical devices. Namely the present invention can beapplied to all those electronic appliances that incorporate such anelectro-optical device as the display section.

Examples of the electronic appliances include a video camera, a digitalcamera, a head mounted display (a goggle type display), a wearabledisplay, a car navigation system, a personal computer and a portableinformation terminal (a mobile computer, a cellular telephone, anelectronic book). FIG. 18A to 18F show examples of these.

FIG. 18A shows a personal computer, which comprises: a main body 2001;an image input section 2002; a display section 2003; and a keyboard2004. The present invention can be applied to the image input section2002, the display section 2003 or other signal driver circuits.

FIG. 18B shows a video camera, which comprises: a main body 2101; adisplay section 2102; a sound input section 2103; an operation switch2104; a battery 2105; and an image receiving section 2106. The presentinvention can be applied to the display section 2102, the sound inputsection 2103 or other signal control circuits.

FIG. 18C shows a mobile computer, which comprises: a main body 2201; acamera section 2202; an image receiving section 2203; an operationswitch 2204; and a display section 2205. The present invention can beapplied to the display section 2205 or other signal driver circuits.

FIG. 18D shows a goggle type display, which comprises: a main body 2301;a display section 2302; and an arm section 2303. The present inventioncan be applied to the display section 2302 or other signal drivercircuits.

FIG. 18E shows a player that uses a recording medium storing a program(hereinafter called the “recording medium”). It comprises a main body2401, a display section 2402, a speaker unit 2403, a recording medium2404 and an operation switch 2405. Note that by using DVD (digitalversatile disc), CD, etc., as a recording medium of this device, musicappreciation, film appreciation, games or the use for Internet can beperformed. The present invention can be applied to the display device2402 and other signal driver circuits.

FIG. 18F shows a digital camera, which comprises: a main body 2501; adisplay section 2502; a view finder section 2503; an operation switch2504; and an image reception unit (not shown). The present invention canbe applied to the display unit 2502 or other signal driver circuits.

As described above, the applicable range of the present invention isvery large, and it can be applied to electronic appliances of variousfields. Further, the electronic appliances of the present Embodiment canbe realized by using constitution of any combination of Embodiments 1 to7.

Embodiment 9

TFTs manufactured by implementing the present invention can be used forvarious electro-optical devices. Namely the present invention can beapplied to all those electronic appliances that incorporate such anelectro-optical device as the display section.

Projectors (rear type or front type) or the like can be given as suchelectronic appliances. The examples are shown in FIGS. 19A to 19D.

FIG. 19A shows a front type projector, which comprises: a projectionsystem 2601; and a screen 2602. The present invention can be applied toa liquid crystal display device 2808 which forms a part of theprojection system 2601, or other signal driver circuits.

FIG. 19B shows a rear type projector, which comprises: a main body 270l;a projection system 2702; a mirror 2703; and a screen 2704. The presentinvention can be applied to the liquid crystal display device 2808 thatconstitutes a part of the projection system 2702, or other signal drivercircuit.

Note that FIG. 19C shows an example of the construction of the displaydevices 2601 and 2702 in FIGS. 19A and 19B. The projection systems 2601and 2702 comprise: a light source optical system 2801; mirrors 2802,2804 to 2806; a dichroic mirror 2803; a prism 2807; a liquid crystaldisplay device 2808; a phase difference plate 2809; and a projectionoptical system 2810. The projection optical system 2810 comprises anoptical system including a projection lens. Though the presentEmbodiment shows an example of the three-plate system, there is nolimitation to such a system, but may be applied to a single-plateoptical system. The operator may appropriately dispose an optical lens,a film having a polarization function, a film for adjusting the phase,an IR film, etc, in the optical path indicated by an arrow in FIG. 19C.

FIG. 19D shows an example of the structure of light source opticalsystem 2801 in FIG. 19C. In this embodiment, the light source opticalsystem 2801 comprises: a reflector 2811; a light source 2812; lensarrays 2813 and 2814; a polarization conversion element 2815; and acondenser lens 2816. Incidentally, the light source optical system shownin FIG. 19D is an example but is in no way restrictive. For example, theoperator may appropriately dispose an optical lens, a film having apolarization function, a film for adjusting the phase, an IR film, etc,in the light source optical system.

As described above, the applicable range of the present invention isvery large, and it can be applied to electronic appliances of variousfields. Further, the electronic appliances of the present Embodiment canbe realized by using constitution of any combination of Embodiments 1 to3 and 7. Provided, however the projectors of the present Embodiment is atransmission type liquid crystal display device and it is needless tosay that they cannot be applied to a reflection type liquid crystaldisplay devices.

By suitably setting the conditions of bias power and specific gas flowrate, which are capable of controlling a taper angle α of a wiring, theselectivity with respect to a base film can be increased and at the sametime, the desired taper angle α can be obtained in accordance with thepresent invention. As a result, the coverage of films formed on thewiring becomes better, and therefore, defects such as wiring chipping,wiring breakage, and short circuits can be reduced.

Further, etching can be performed with good distribution within thesection, and a uniform wiring shape can be obtained.

Furthermore, the present invention can be applied to the openingprocesses of a contact hole etc.

1-31. Cancel
 32. A display device comprising: a substrate; a firstN-channel thin film transistor formed over the substrate, said firstN-channel thin film transistor comprising: a first semiconductor islandincluding at least a first channel region, a second channel region,lightly doped regions and source and drain regions; a first gateinsulator formed over the first semiconductor island; a first gateelectrode formed over the first channel region with the first gateinsulator interposed therebetween; and a second gate electrode formedover the second channel region with the first gate insulator interposedtherebetween; a driver circuit including at least one second N-channeltype thin film transistor formed over the substrate, said secondN-channel type thin film transistor comprising: a second semiconductorisland including at least a third channel region; a second gateinsulator formed over the second semiconductor island; a third gateelectrode formed over the third channel region with the second gateinsulator interposed therebetween; a blocking insulating film coveringthe first, second and third gate electrodes and said the first andsecond semiconductor islands, said blocking insulating film comprisingsilicon nitride; and a pixel electrode formed over the blockinginsulating film and electrically connected to one of the source anddrain regions of the first semiconductor island, wherein each of thefirst, second and third gate electrodes has tapered edges with a taperangle of in the range of 20° to 70°.
 33. The display device according toclaim 32 wherein each of said first, second and third gate electrodescomprises tungsten or an alloy thereof.
 34. The display device accordingto claim 32 wherein each of said first, second and third gate electrodescomprises a material selected from the group consisting of Ta, Ti, Mo,Cr, Nb and Si.
 35. The display device according to claim 32 wherein saidpixel electrode comprises zinc oxide.
 36. The display device accordingto claim 32 wherein said taper angle is in the range of 25° to 35°. 37.The display device according to claim 32 further comprising a base filmcomprising silicon oxynitride film between said substrate and said firstand second N-channel type thin film transistors.
 38. The display deviceaccording to claim 32 wherein said gate insulator comprises siliconoxynitride.
 39. A display device comprising: a substrate; a firstN-channel thin film transistor formed over the substrate, said firstN-channel thin film transistor comprising: a first semiconductor islandincluding at least a first channel region, a second channel region,lightly doped regions and source and drain regions; a first gateinsulator formed over the first semiconductor island; a first gateelectrode formed over the first channel region with the first gateinsulator interposed therebetween; and a second gate electrode formedover the second channel region with the first gate insulator interposedtherebetween; a driver circuit including at least one second N-channeltype thin film transistor formed over the substrate, said secondN-channel type thin film transistor comprising: a second semiconductorisland including at least a third channel region; a second gateinsulator formed over the second semiconductor island; a third gateelectrode formed over the third channel region with the second gateinsulator interposed therebetween; a blocking insulating film coveringthe first, second and third gate electrodes and said the first andsecond semiconductor islands, said blocking insulating film comprisingsilicon nitride; and a pixel electrode formed over the blockinginsulating film and electrically connected to one of the source anddrain regions of the first semiconductor island, wherein each of thefirst, second and third gate electrodes has tapered edges with a taperangle of in the range of 20° to 70°, wherein each of said lightly dopedregions is overlapped by the tapered edges of the first and second gateelectrodes at least partly.
 40. The display device according to claim 39wherein each of said first, second and third gate electrodes comprisestungsten or an alloy thereof.
 41. The display device according to claim39 wherein each of said first, second and third gate electrodescomprises a material selected from the group consisting of Ta, Ti, Mo,Cr, Nb and Si.
 42. The display device according to claim 39 wherein saidpixel electrode comprises zinc oxide.
 43. The display device accordingto claim 39 wherein said taper angle is in the range of 25° to 35°. 44.The display device according to claim 39 further comprising a base filmcomprising silicon oxynitride film between said substrate and said firstand second N-channel type thin film transistors.
 45. The display deviceaccording to claim 39 wherein said gate insulator comprises siliconoxynitride.
 46. A display device comprising: a substrate; a firstN-channel thin film transistor formed over the substrate, said firstN-channel thin film transistor comprising: a first semiconductor islandincluding at least a first channel region, a second channel region, anda capacitor forming region; a first gate insulator formed over the firstsemiconductor island; a first gate electrode formed over the firstchannel region with the first gate insulator interposed therebetween; asecond gate electrode formed over the second channel region with thefirst gate insulator interposed therebetween; a driver circuit includingat least one second N-channel type thin film transistor formed over thesubstrate, said second N-channel type thin film transistor comprising: asecond semiconductor island including at least a third channel region;and a third gate electrode formed over the third channel region with thesecond gate insulator interposed therebetween; a capacitor electrodeformed over the capacitor forming region of the first semiconductorisland with an insulator interposed therebetween; a blocking insulatingfilm covering the first, second and third gate electrodes and said thefirst and second semiconductor islands, said blocking insulating filmcomprising silicon nitride; a pixel electrode formed over the blockinginsulating film and electrically connected to an impurity region of thefirst semiconductor island, wherein each of the first, second and thirdgate electrodes and said capacitor electrode has tapered edges with ataper angle of in the range of 20° to 70°.
 47. The display deviceaccording to claim 46 wherein each of said first, second and third gateelectrodes comprises tungsten or an alloy thereof.
 48. The displaydevice according to claim 46 wherein each of said first, second andthird gate electrodes comprises a material selected from the groupconsisting of Ta, Ti, Mo, Cr, Nb and Si.
 49. The display deviceaccording to claim 46 wherein said pixel electrode comprises zinc oxide.50. The display device according to claim 46 wherein said taper angle isin the range of 25° to 35°.
 51. The display device according to claim 46further comprising a base film comprising silicon oxynitride filmbetween said substrate and said first and second N-channel type thinfilm transistors.
 52. The display device according to claim 46 whereinsaid gate insulator comprises silicon oxynitride.
 53. A display devicecomprising: a substrate; a first N-channel thin film transistor formedover the substrate, said first N-channel thin film transistorcomprising: a first semiconductor island including at least a firstchannel region, a second channel region, lightly doped regions andsource and drain regions; a first gate insulator formed over the firstsemiconductor island; a first gate electrode formed over the firstchannel region with the first gate insulator interposed therebetween;and a second gate electrode formed over the second channel region withthe first gate insulator interposed therebetween; a driver circuitincluding at least one second N-channel type thin film transistor formedover the substrate, said second N-channel type thin film transistorcomprising: a second semiconductor island including at least a thirdchannel region; a second gate insulator formed over the secondsemiconductor island; a third gate electrode formed over the thirdchannel region with the second gate insulator interposed therebetween; ablocking insulating film covering the first, second and third gateelectrodes and said the first and second semiconductor islands, saidblocking insulating film comprising silicon nitride; and a pixelelectrode formed over the blocking insulating film and electricallyconnected to one of the source and drain regions of the firstsemiconductor island, wherein each of the first, second and third gateelectrodes has tapered edges with a taper angle of in the range of 20°to 70°, wherein first portions of the first gate insulator covered bysaid first and second gate electrodes are thicker than second portionsof the first gate insulator not covered by said first and second gateelectrodes.
 54. The display device according to claim 53 wherein each ofsaid first, second and third gate electrodes comprises tungsten or analloy thereof.
 55. The display device according to claim 53 wherein eachof said first, second and third gate electrodes comprises a materialselected from the group consisting of Ta, Ti, Mo, Cr, Nb and Si.
 56. Thedisplay device according to claim 53 wherein said pixel electrodecomprises zinc oxide.
 57. The display device according to claim 53wherein said taper angle is in the range of 25° to 35°.
 58. The displaydevice according to claim 53 further comprising a base film comprisingsilicon oxynitride film between said substrate and said first and secondN-channel type thin film transistors.
 59. The display device accordingto claim 53 wherein said gate insulator comprises silicon oxynitride.60. A display device comprising: a substrate; a first N-channel thinfilm transistor formed over the substrate, said first N-channel thinfilm transistor comprising: a first semiconductor island including atleast a first channel region, a second channel region, lightly dopedregions and source and drain regions; a first gate insulator formed overthe first semiconductor island; a first gate electrode formed over thefirst channel region with the first gate insulator interposedtherebetween; and a second gate electrode formed over the second channelregion with the first gate insulator interposed therebetween; a drivercircuit including at least one second N-channel type thin filmtransistor formed over the substrate, said second N-channel type thinfilm transistor comprising: a second semiconductor island including atleast a third channel region; a second gate insulator formed over thesecond semiconductor island; a third gate electrode formed over thethird channel region with the second gate insulator interposedtherebetween; a blocking insulating film covering the first, second andthird gate electrodes and said the first and second semiconductorislands, said blocking insulating film comprising silicon nitride; and apixel electrode formed over the blocking insulating film andelectrically connected to one of the source and drain regions of thefirst semiconductor island, wherein each of the first, second and thirdgate electrodes has tapered edges with a taper angle of in the range of20° to 70°, wherein each of said lightly doped regions is overlapped bythe tapered edges of the first and second gate electrodes at leastpartly, and wherein first portions of the first gate insulator coveredby said first and second gate electrodes are thicker than secondportions of the first gate insulator not covered by said first andsecond gate electrodes.
 61. The display device according to claim 60wherein each of said first, second and third gate electrodes comprisestungsten or an alloy thereof.
 62. The display device according to claim60 wherein each of said first, second and third gate electrodescomprises a material selected from the group consisting of Ta, Ti, Mo,Cr, Nb and Si.
 63. The display device according to claim 60 wherein saidpixel electrode comprises zinc oxide.
 64. The display device accordingto claim 60 wherein said taper angle is in the range of 25° to 35°. 65.The display device according to claim 60 further comprising a base filmcomprising silicon oxynitride film between said substrate and said firstand second N-channel type thin film transistors.
 66. The display deviceaccording to claim 60 wherein said gate insulator comprises siliconoxynitride.
 67. A display device comprising: a substrate; a firstN-channel first thin film transistor formed over the substrate, saidfirst N-channel thin film transistor comprising: a first semiconductorisland including at least a first channel region, a second channelregion, and a capacitor forming region; a first gate insulator formedover the first semiconductor island; a first gate electrode formed overthe first channel region with the first gate insulator interposedtherebetween; a second gate electrode formed over the second channelregion with the first gate insulator interposed therebetween; a drivercircuit including at least one second N-channel type thin filmtransistor formed over the substrate, said second N-channel type thinfilm transistor comprising: a second semiconductor island including atleast a third channel region; and a third gate electrode formed over thethird channel region with the second gate insulator interposedtherebetween; a capacitor electrode formed over the capacitor formingregion of the first semiconductor island with an insulator interposedtherebetween; a blocking insulating film covering the first, second andthird gate electrodes and said the first and second semiconductorislands, said blocking insulating film comprising silicon nitride; apixel electrode formed over the blocking insulating film andelectrically connected to an impurity region of the first semiconductorisland, wherein each of the first, second and third gate electrodes andsaid capacitor electrode has tapered edges with a taper angle of in therange of 20° to 70°, and wherein first portions of the first gateinsulator covered by said first and second gate electrodes are thickerthan second portions of the first gate insulator not covered by saidfirst and second gate electrodes.
 68. The display device according toclaim 67 wherein each of said first, second and third gate electrodescomprises tungsten or an alloy thereof.
 69. The display device accordingto claim 67 wherein each of said first, second and third gate electrodescomprises a material selected from the group consisting of Ta, Ti, Mo,Cr, Nb and Si.
 70. The display device according to claim 67 wherein saidpixel electrode comprises zinc oxide.
 71. The display device accordingto claim 67 wherein said taper angle is in the range of 25° to 35°. 72.The display device according to claim 67 further comprising a base filmcomprising silicon oxynitride film between said substrate and said firstand second N-channel type thin film transistors.
 73. The display deviceaccording to claim 67 wherein said gate insulator comprises siliconoxynitride.
 74. A display device comprising: a substrate; a firstN-channel thin film transistor formed over the substrate, said firstN-channel thin film transistor comprising: a first N-channel thin filmtransistor formed over the substrate, said first N-channel thin filmtransistor comprising: a first semiconductor island including at least afirst channel region, a second channel region, lightly doped regions andsource and drain regions; a first gate insulator formed over the firstsemiconductor island; a first gate electrode formed over the firstchannel region with the first gate insulator interposed therebetween;and a second gate electrode formed over the second channel region withthe first gate insulator interposed therebetween; a driver circuitincluding at least one second N-channel type thin film transistor formedover the substrate, said second N-channel type thin film transistorcomprising: a second semiconductor island including at least a thirdchannel region; a third gate electrode formed over the third channelregion with the second gate insulator interposed therebetween; ablocking insulating film covering the first, second and third gateelectrodes and said the first and second semiconductor islands, saidblocking insulating film comprising silicon nitride; and an interlayerinsulating film comprising an organic resin formed over said blockinginsulating film; and a pixel electrode formed over the interlayerinsulating film and electrically connected to one of the source anddrain regions of the first semiconductor island, wherein each of thefirst, second and third gate electrodes has tapered edges with a taperangle of in the range of 20° to 70°.
 75. The display device according toclaim 74 wherein each of said first, second and third gate electrodescomprises tungsten or an alloy thereof.
 76. The display device accordingto claim 74 wherein each of said first, second and third gate electrodescomprises a material selected from the group consisting of Ta, Ti, Mo,Cr, Nb and Si.
 77. The display device according to claim 74 wherein saidpixel electrode comprises zinc oxide.
 78. The display device accordingto claim 74 wherein said taper angle is in the range of 25° to 35°. 79.The display device according to claim 74 further comprising a base filmcomprising silicon oxynitride film between said substrate and said firstand second N-channel type thin film transistors.
 80. The display deviceaccording to claim 74 wherein said gate insulator comprises siliconoxynitride.
 81. The display device according to claim 74 wherein saidorganic resin comprises a material selected from the group consisting ofpolyimide, acrylic, poliamide, polyimide amide and BCB.
 82. A displaydevice comprising: a substrate; a first N-channel first thin filmtransistor formed over the substrate, said first N-channel thin filmtransistor comprising: a first N-channel thin film transistor formedover the substrate, said first N-channel thin film transistorcomprising: a first semiconductor island including at least a firstchannel region, a second channel region, lightly doped regions andsource and drain regions; a first gate insulator formed over the firstsemiconductor island; a first gate electrode formed over the firstchannel region with the first gate insulator interposed therebetween;and a second gate electrode formed over the second channel region withthe first gate insulator interposed therebetween; a driver circuitincluding at least one second N-channel type thin film transistor formedover the substrate, said second N-channel type thin film transistorcomprising: a second semiconductor island including at least a thirdchannel region; a third gate electrode formed over the third channelregion with the second gate insulator interposed therebetween; ablocking insulating film covering the first, second and third gateelectrodes and said the first and second semiconductor islands, saidblocking insulating film comprising silicon nitride; an interlayerinsulating film comprising an organic resin formed over said blockinginsulating film; and a pixel electrode formed over the interlayerinsulating film and electrically connected to one of the source anddrain regions of the first semiconductor island, wherein each of thefirst, second and third gate electrodes has tapered edges with a taperangle of in the range of 20° to 70°, wherein each of said lightly dopedregions is overlapped by the tapered edges of the first and second gateelectrodes at least partly.
 83. The display device according to claim 82wherein each of said first, second and third gate electrodes comprisestungsten or an alloy thereof.
 84. The display device according to claim82 wherein each of said first, second and third gate electrodescomprises a material selected from the group consisting of Ta, Ti, Mo,Cr, Nb and Si.
 85. The display device according to claim 82 wherein saidpixel electrode comprises zinc oxide.
 86. The display device accordingto claim 82 wherein said taper angle is in the range of 25° to 35°. 87.The display device according to claim 82 further comprising a base filmcomprising silicon oxynitride film between said substrate and said firstand second N-channel type thin film transistors.
 88. The display deviceaccording to claim 82 wherein said gate insulator comprises siliconoxynitride.
 89. The display device according to claim 82 wherein saidorganic resin comprises a material selected from the group consisting ofpolyimide, acrylic, poliamide, polyimide amide and BCB.
 90. A displaydevice comprising: a substrate; a first N-channel first thin filmtransistor formed over the substrate, said first N-channel thin filmtransistor comprising: a first semiconductor island including at least afirst channel region, a second channel region, and a capacitor formingregion; a first gate insulator formed over the first semiconductorisland; a first gate electrode formed over the first channel region withthe first gate insulator interposed therebetween; a second gateelectrode formed over the second channel region with the first gateinsulator interposed therebetween; a driver circuit including at leastone second N-channel type thin film transistor formed over thesubstrate, said second N-channel type thin film transistor comprising: asecond semiconductor island including at least a third channel region;and a third gate electrode formed over the third channel region with thesecond gate insulator interposed therebetween; a capacitor electrodeformed over the capacitor forming region of the first semiconductorisland with an insulator interposed therebetween; a blocking insulatingfilm covering the first, second and third gate electrodes and said thefirst and second semiconductor islands, said blocking insulating filmcomprising silicon nitride; an interlayer insulating film comprising anorganic resin formed over said blocking insulating film; and a pixelelectrode formed over the interlayer insulating film and electricallyconnected to an impurity region of the first semiconductor island,wherein each of the first, second and third gate electrodes and saidcapacitor electrode has tapered edges with a taper angle of in the rangeof 20° to 70°.
 91. The display device according to claim 90 wherein eachof said first, second and third gate electrodes comprises tungsten or analloy thereof.
 92. The display device according to claim 90 wherein eachof said first, second and third gate electrodes comprises a materialselected from the group consisting of Ta, Ti, Mo, Cr, Nb and Si.
 93. Thedisplay device according to claim 90 wherein said pixel electrodecomprises zinc oxide.
 94. The display device according to claim 90wherein said taper angle is in the range of 25° to 35°.
 95. The displaydevice according to claim 90 further comprising a base film comprisingsilicon oxynitride film between said substrate and said first and secondN-channel type thin film transistors.
 96. The display device accordingto claim 90 wherein said gate insulator comprises silicon oxynitride.97. The display device according to claim 90 wherein said organic resincomprises a material selected from the group consisting of polyimide,acrylic, poliamide, polyimide amide and BCB.
 98. A display devicecomprising: a substrate; a first N-channel first thin film transistorformed over the substrate, said first N-channel thin film transistorcomprising: a first N-channel thin film transistor formed over thesubstrate, said first N-channel thin film transistor comprising: a firstsemiconductor island including at least a first channel region, a secondchannel region, lightly doped regions and source and drain regions; afirst gate insulator formed over the first semiconductor island; a firstgate electrode formed over the first channel region with the first gateinsulator interposed therebetween; and a second gate electrode formedover the second channel region with the first gate insulator interposedtherebetween; a driver circuit including at least one second N-channeltype thin film transistor formed over the substrate, said secondN-channel type thin film transistor comprising: a second semiconductorisland including at least a third channel region; a third gate electrodeformed over the third channel region with the second gate insulatorinterposed therebetween; a blocking insulating film covering the first,second and third gate electrodes and said the first and secondsemiconductor islands, said blocking insulating film comprising siliconnitride; an interlayer insulating film comprising an organic resinformed over said blocking insulating film; and a pixel electrode formedover the interlayer insulating film and electrically connected to one ofthe source and drain regions of the first semiconductor island, whereineach of the first, second and third gate electrodes has tapered edgeswith a taper angle of in the range of 20° to 70°, wherein first portionsof the first gate insulator covered by said first and second gateelectrodes are thicker than second portions of the first gate insulatornot covered by said first and second gate electrodes.
 99. 1 The displaydevice according to claim 98 wherein each of said first, second andthird gate electrodes comprises tungsten or an alloy thereof.
 100. Thedisplay device according to claim 98 wherein each of said first, secondand third gate electrodes comprises a material selected from the groupconsisting of Ta, Ti, Mo, Cr, Nb and Si.
 101. The display deviceaccording to claim 98 wherein said pixel electrode comprises zinc oxide.102. The display device according to claim 98 wherein said taper angleis in the range of 25° to 35°.
 103. The display device according toclaim 98 further comprising a base film comprising silicon oxynitridefilm between said substrate and said first and second N-channel typethin film transistors.
 104. The display device according to claim 98wherein said gate insulator comprises silicon oxynitride.
 105. Thedisplay device according to claim 98 wherein said organic resincomprises a material selected from the group consisting of polyimide,acrylic, poliamide, polyimide amide and BCB.
 106. A display devicecomprising: a substrate; a first N-channel first thin film transistorformed over the substrate, said first N-channel thin film transistorcomprising: a first N-channel thin film transistor formed over thesubstrate, said first N-channel thin film transistor comprising: a firstsemiconductor island including at least a first channel region, a secondchannel region, lightly doped regions and source and drain regions; afirst gate insulator formed over the first semiconductor island; a firstgate electrode formed over the first channel region with the first gateinsulator interposed therebetween; and a second gate electrode formedover the second channel region with the first gate insulator interposedtherebetween; a driver circuit including at least one second N-channeltype thin film transistor formed over the substrate, said secondN-channel type thin film transistor comprising: a second semiconductorisland including at least a third channel region; a third gate electrodeformed over the third channel region with the second gate insulatorinterposed therebetween; a blocking insulating film covering the first,second and third gate electrodes and said the first and secondsemiconductor islands, said blocking insulating film comprising siliconnitride; an interlayer insulating film comprising an organic resinformed over said blocking insulating film; and a pixel electrode formedover the interlayer insulating film and electrically connected to one ofthe source and drain regions of the first semiconductor island, whereineach of the first, second and third gate electrodes has tapered edgeswith a taper angle of in the range of 20° to 70°, wherein each of saidlightly doped regions is overlapped by the tapered edges of the firstand second gate electrodes at least partly, and wherein first portionsof the first gate insulator covered by said first and second gateelectrodes are thicker than second portions of the first gate insulatornot covered by said first and second gate electrodes.
 107. The displaydevice according to claim 106 wherein each of said first, second andthird gate electrodes comprises tungsten or an alloy thereof.
 108. Thedisplay device according to claim 106 wherein each of said first, secondand third gate electrodes comprises a material selected from the groupconsisting of Ta, Ti, Mo, Cr, Nb and Si.
 109. The display deviceaccording to claim 106 wherein said pixel electrode comprises zincoxide.
 110. The display device according to claim 106 wherein said taperangle is in the range of 25° to 35°.
 111. The display device accordingto claim 106 further comprising a base film comprising siliconoxynitride film between said substrate and said first and secondN-channel type thin film transistors.
 112. The display device accordingto claim 106 wherein said gate insulator comprises silicon oxynitride.113. The display device according to claim 106 wherein said organicresin comprises a material selected from the group consisting ofpolyimide, acrylic, poliamide, polyimide amide and BCB.
 114. A displaydevice comprising: a substrate; a first N-channel first thin filmtransistor formed over the substrate, said first N-channel thin filmtransistor comprising: a first semiconductor island including at least afirst channel region, a second channel region, and a capacitor formingregion; a first gate insulator formed over the first semiconductorisland; a first gate electrode formed over the first channel region withthe first gate insulator interposed therebetween; a second gateelectrode formed over the second channel region with the first gateinsulator interposed therebetween; a driver circuit including at leastone second N-channel type thin film transistor formed over thesubstrate, said second N-channel type thin film transistor comprising: asecond semiconductor island including at least a third channel region;and a third gate electrode formed over the third channel region with thesecond gate insulator interposed therebetween; a capacitor electrodeformed over the capacitor forming region of the first semiconductorisland with an insulator interposed therebetween; a blocking insulatingfilm covering the first, second and third gate electrodes and said thefirst and second semiconductor islands, said blocking insulating filmcomprising silicon nitride; an interlayer insulating film comprising anorganic resin formed over said blocking insulating film; and a pixelelectrode formed over the interlayer insulating film and electricallyconnected to an impurity region of the first semiconductor island,wherein each of the first, second and third gate electrodes and saidcapacitor electrode has tapered edges with a taper angle of in the rangeof 20° to 70°, and wherein first portions of the first gate insulatorcovered by said first and second gate electrodes are thicker than secondportions of the first gate insulator not covered by said first andsecond gate electrodes
 115. The display device according to claim 114wherein each of said first, second and third gate electrodes comprisestungsten or an alloy thereof.
 116. The display device according to claim114 wherein each of said first, second and third gate electrodescomprises a material selected from the group consisting of Ta, Ti, Mo,Cr, Nb and Si.
 117. The display device according to claim 114 whereinsaid pixel electrode comprises zinc oxide.
 118. The display deviceaccording to claim 114 wherein said taper angle is in the range of 25°to 35°.
 119. The display device according to claim 114 furthercomprising a base film comprising silicon oxynitride film between saidsubstrate and said first and second N-channel type thin filmtransistors.
 120. The display device according to claim 114 wherein saidgate insulator comprises silicon oxynitride.
 121. The display deviceaccording to claim 114 wherein said organic resin comprises a materialselected from the group consisting of polyimide, acrylic, poliamide,polyimide amide and BCB.